The present invention relates to a phase locked loop circuit (hereinafter referred to as xe2x80x9cPLL circuitxe2x80x9d) for generating an output signal having no lags in frequency and phase from those of an input signal, which is used in a magnetic disk unit such as an optical disk unit.
A recent CD (Compact Disk) player is capable of normal-speed playback when reading audio data from a CD, and 32X-speed playback when reading computer data from a CD. In such CD player capable of playing both of a CD containing audio data and a CD containing computer data, when playing the disk at 32X speed, the maximum frequency of the reproduced data pulse read from the disk becomes 32 times as high as that at the normal-speed playback and, therefore, the frequency of a clock generated in phase-synchronization with the reproduced data also becomes 32 times as high as that at the normal-speed playback. That is, the frequency bands of clocks handled by one CD player extend widely.
Further, in the CD player capable of the high-speed playback mentioned above, there is a difference in the maximum frequency components of the reproduced data pulses between playback of data recorded on the inner radius of the disk and playback of data recorded on the outer radius of the disk.
For this reason, the range of frequencies oscillated by a VCO (Voltage Controlled Oscillator), which is provided in a PLL circuit for generating a clock to read disk data, is also wide.
Accordingly, a PLL circuit included in the CD player having the above-mentioned high-speed playback function is required to quickly respond to a wide range of frequency bands handled in the CD player, and conventionally, a PLL circuit provided with a frequency comparator is employed to meet this requirement. FIG. 3 shows a PLL circuit provided with a frequency comparator (hereinafter referred to as xe2x80x9cPLL circuit Xxe2x80x9d).
The conventional PLL circuit X comprises a frequency comparator 1, a phase comparator 2, a first charge pump 4, and second charge pump 5, a loop filter 6, and a VCO 7.
The frequency comparator 1 included in the conventional PLL circuit X brings a clock generated by the VCO 7 up to a range where the phase comparator 2 can synchronize the phase of the reproduced data pulse and the phase of the clock generated by the VCO 7, i.e., a range where the phase comparator 2 can lock the phases. Once the phases are locked, the clock generated by the VCO 7 is prevented from being adversely affected by the output of the frequency comparator 1, using a signal to halt the operation of the frequency comparator 1.
In the aforementioned PLL circuit X, however, since the range of adaptable frequency bands is broad, fluctuations in the output from the first charge pump 4 for controlling the VCO 7 according to the output of the frequency comparator 1 are increased, whereby the range of fluctuations in the output from the loop filter 6 for smoothing the output of the first charge pump 4 becomes wide, resulting in an unstable PLL circuit.
To be specific, the frequency of the clock generated by the VCO 7 changes in proportion with the output voltage of the loop filter 6. So, in order to bring the clock generated by the VCO 7 into phase-synchronization with the reproduced data pulse quickly, the frequency of the clock generated by the VCO 7 must be increased or decreased quickly in a stroke.
Furthermore, when the reproduced data pulse has a large amount of jitter, the frequency comparator 1 generates jitters in the clock generated by the VCO 7 in response to the clock jitters of the reproduced data pulse. As the result, the phase comparator 2 cannot lock the phases.
The present invention is made to solve the above-described problems and has for its object to provide a PLL circuit which can limit the operation of a frequency comparator with its output when a difference in phases between reproduced data pulse and VCO clock is in the pull-in range of the phase comparator, and lock the phases even when the reproduced data pulse has a large amount of jitter, thereby performing stable data reading.
Other objects and advantages of the invention will be apparent from the detailed description that follows. The detailed description and specific embodiment described are provided only for illustration since various additions and modifications within the scope of the invention will be apparent to those of skill in the art from the detailed description.
According to a first aspect of the present invention, there is provided a PLL circuit used in a magnetic disk unit, which generates a clock in phase-synchronization with a reproduced data pulse read from the magnetic disk. The phase locked loop circuit comprises a frequency comparator for detecting a phase difference based on a difference in frequencies between the reproduced data pulse and the clock, and outputting a frequency error level which is the result of detection, as a frequency comparison error signal; a phase comparator for detecting a difference in phases between the reproduced data pulse and the clock; a selector for outputting the frequency comparison error signal as it is when the frequency error level is relatively large, and thinning the frequency comparison error signal to be output when the frequency error level is relatively small; a first charge pump for increasing/decreasing the output voltage on the basis of the output from the selector; a second charge pump for increasing/decreasing the output voltage on the basis of the output from the phase comparator; a loop filter for eliminating unnecessary components included in a signal obtained by adding the output from the first charge pump and the output from the second charge pump; and a voltage controlled oscillator for generating a clock of a frequency corresponding to the output voltage of the loop filter. Therefore, even when the reproduced data pulse has a large amount of clock jitter, a PLL circuit capable of speedy and stable data reading operation is obtained.
According to a second aspect of the present invention, in the above-described PLL circuit, the frequency comparator detects phase sections of the clock corresponding to a leading edge and a trailing edge of the reproduced data pulse to perform frequency comparison, and outputs the result of comparison as a frequency comparison error signal; and the selector thins the frequency comparison error signal to be output when there is a change between specific phase sections of the clock, which correspond to the leading edge and trailing edge of the reproduced data pulse, respectively, and are detected by the frequency comparator. Therefore, assuming that the phase sections of the clock are xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c2xe2x80x9d, and xe2x80x9c3xe2x80x9d, when the phase section of the clock corresponding to the data edge changes from xe2x80x9c1xe2x80x9d to xe2x80x9c0xe2x80x9d, or from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d, the edge of the reproduced data pulse is regarded as being fluctuated by signal jitter. In this case, the output from the frequency comparator is controlled so as not to fluctuate the frequency of the VCO, whereby unnecessary frequency fluctuation does not occur in the output of the VCO, resulting in stable data reproduction.